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FM8PE513M产品描述：
2.1.4 STATUS (Status Register)
Read/Write-POR R/W-0 R/W-0 R/W-0 R-# R-# R/W-x R/W-x R/W-x
Address Name B7 B6 B5 B4 B3 B2 B1 B0
PD
0x03 STATUS RST - TO --- ---- Z DC C
Legend: x = unknown, # refer Table 2.3 for detail description, more bits default state, please refer to Table 2.2.
This register contains the arithmetic status of the ALU, the RESET status.
If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these
three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits
are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different
than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS
Register as 000u u1uu (where u = unchanged).
C : Carry/borrow bit.
ADDAR, ADDIA
= 1, Carry occurred.
= 0, No Carry occurred.
SUBAR, SUBIA
= 1, No borrow occurred.
= 0, Borrow occurred.
Note : A subtraction is by adding the two’s complement of the second operand. For rotate (RRR, RLR)
instructions, this bit is loaded with either the high or low order bit of the source register.
DC : Half carry/half borrow bit
ADDAR, ADDIA
= 1, Carry from the 4th low order bit of the result occurred.
= 0, No Carry from the 4th low order bit of the result occurred.
SUBAR, SUBIA
= 1, No Borrow from the 4th low order bit of the result occurred.
= 0, Borrow from the 4th low order bit of the result occurred.
Z : Zero bit.
= 1, The result of a logic operation is zero.
= 0, The result of a logic operation is not zero.
PD : Power down flag bit.
= 1, after power-up or by the CLRWDT instruction.
= 0, by the SLEEP instruction.
TO : Time overflow flag bit.
= 1, after power-up or by the CLRWDT or SLEEP instruction
= 0, a watch-dog time overflow occurred
RST : Bit for wake-up type.
= 1, Wake-up from SLEEP on Port B input change.
= 0, Wake-up from other reset types.