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MFRC50001T 0FE,112 MKE02Z

  • 发布时间:2022-03-31 12:12:01
    报价:面议
    地址:广东,深圳,深圳市福田区赛格电子科技大厦
    公司:深圳市斯瑞特科技有限公司

    手机:13560767759
    微信:zhouyianmei
    电话:0755-29309513
    用户等级:普通会员

    capability to both receive and send information (such as memory). Transmitters and/or

    receivers can operate in either master or slave mode, depending on whether the chip has

    to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be

    controlled by more than one bus master.

    The I2C0-bus functions are fixed-pin functions. All other I2C-bus functions for I2C1/2/3

    are movable functions and can be assigned through the switch matrix to any pin.

    However, only the true open-drain pins provide the electrical characteristics to support the

    full I2C-bus specification (see Ref. 3).

    8.15.1 Features

    • I2C0 supports Fast-mode Plus with data rates of up to 1 Mbit/s in addition to standard

    and fast modes on two true open-drain pins.

    • True open-drain pins provide fail-safe operation: When the power to an I2C-bus

    device is switched off, the SDA and SCL pins connected to the I2C0-bus are floating

    and do not disturb the bus.

    • I2C1/2/3 support standard and fast mode with data rates of up to 400 kbit/s.

    • Independent Master, Slave, and Monitor functions.

    • Supports both Multi-master and Multi-master with Slave functions.

    • Multiple I2C slave addresses supported in hardware.

    • One slave address can be selectively qualified with a bit mask or an address range in

    order to respond to multiple I2C bus addresses.

    • 10-bit addressing supported with software assist.

    • Supports SMBus.

    8.16 SCTimer/PWM

    The state configurable timer can perform basic 16-bit and 32-bit timer/counter functions

    with match outputs and external and internal capture inputs. In addition, the

    SCTimer/PWM can employ up to eight different programmable states, which can change

    under the control of events, to provide complex timing patterns.

    The inputs to the SCT are multiplexed between movable functions from the switch matrix

    and internal connections such as the ADC threshold compare interrupt, the comparator

    output, and the ARM core signals ARM_TXEV and DEBUG_HALTED. The signal on each

    SCT input is selected through the INPUT MUX.

    All outputs of the SCT are movable functions and are assigned to pins through the switch

    matrix. One SCT output can also be selected as one of the ADC conversion triggers.

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