1 General Description
The EM78P153K is an 8-bit microprocessor designed and developed with low-power and high-speed
CMOS technology. The device has an on-chip 1024 × 13-bit Electrical One Time Programmable Read
Only Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user’s OTP memory
code. Fifteen Code option bits are also available to meet user’s requirements.
With enhanced OTP-ROM features, the EM78P153K provides a convenient way of developing and
verifying user’s programs. Moreover, this OTP device offers the advantages of easy and effective
program updates, using development and programming tools. You can avail of the ELAN Writer to
easily program your development code.
2 Features
CPU configuration
• 1k × 13 bits on chip ROM
• 32 × 8 bits on-chip registers (SRAM, general
purpose)
• 5 level stacks for subroutine nesting
• 3 programmable level voltage reset LVR :
4.0, 3.5, 2.7V
• Less than 1.5 mA at 5V / 4MHz
• 15 μA at 3V/32kHz (Typical)
• 1 μA during Sleep mode (Typical)
I/O port configuration
• 2 bidirectional I/O ports : P5, P6
• 12 I/O pins
• Wake-up port : P6
• 6 Programmable pull-down I/O pins
• 7 programmable pull-high I/O pins
• 7 programmable open-drain I/O pins
• External interrupt : P60
Operating voltage range:
• 2.1V ~ 5.5V at 0 ~ 70°C (Commercial)
• 2.3V ~ 5.5V at -40 ~ 85°C (Industrial)
Operating frequency range (base on 2 clocks):
• Crystal mode:
DC ~ 20MHz / 2clks @ 5V
DC ~ 8MHz / 2clks @ 3V
DC ~ 4MHz / 2clks @ 2.1V
• ERC mode:
DC ~ 2MHz / 2clks @ 2.1V
• IRC mode:
Peripheral configuration
• 8-bit real time clock/counter (TCC) with
selective signal sources, trigger edges, and
overflow interrupt
• 2- / 4 clocks per instruction cycle selected by
code option
• High EFT immunity
Three available interrupts:
• TCC overflow interrupt
• Input-port status changed interrupt (wake-up
from sleep mode)
• External interrupt
Special features
• Programmable free running watchdog timer
• Power saving sleep mode
• Selectable oscillation mode
• Programmable prescaler of oscillator set-up
time
Package type:
• 14-pin DIP 300mil : EM78P153KD14J
• 14-pin SOP 150mil : EM78P153KSO14J
Note: These are all green products which do not
contain hazardous substances.
5.1 Operational Registers
5.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing
pointer. Any instruction using R0 as a pointer actually accesses data pointed by the
RAM Select Register (R4).
5.1.2 R1 (Timer Clock/Counter)
Incremented by an external signal edge, which is defined by TE bit (CONT-4)
through the TCC pin, or by the instruction cycle clock.
Writable and readable as any other registers.
Defined by resetting PAB (CONT-3).
The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
The contents of the prescaler counter will be cleared only when the TCC register is
written with a value.
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